A memory controller manages the flow of data between a processor and a one or more memory modules on an interface or bus. The memory controller contains the logic needed to read and write to a memory module and refresh the data stored in the DRAM is implemented as a separate chip. The memory controller supports a protocol used by multiple memory modules coupled to the channel, such as the Joint Electron Device Engineering Council (JEDEC) Double Data Rate Third Generation (DDR3) Synchronous Dynamic Random Access Memory (SDRAM) protocol.
Before using the interface to memory, the memory controller must configure the memory modules for operations by adjusting the timing at which the memory controller will activate to sample read data from the memory modules. A signal alignment device, such as a phase interpolator, is controlled by the memory controller to generate clock phase information and is responsive to phase control signals and reference signals having different determined phases to align the data sampling signal to sample the read data center at the center at which the read data will be transmitted or the data eye.